The manufacture and design of integrated circuits has greatly increased in sophistication in recent years, particularly in regard to the increase of current density. Increased integration density leads to economic advantages as an increased number of devices and circuits are placed on a single chip and/or within a single package (which may include a plurality of chips). Performance improvements such as, for example, reduced signal propagation time and noise immunity can typically be achieved as integration density is increased due to a reduction in the length of signal paths and reduction in capacitance between connections. This performance gain is particularly important in integrated circuits (ICs).
ICs such as dynamic random access memory (DRAM) can have millions of similar devices on a single chip (often collectively referred to as an array or an array portion of the chip design) which are controlled throughout the chip portions thereof by circuits such as addressing circuits, sense amplifiers and the like, generally referred to as support circuits. Unfortunately, the circuit requirements are generally different for the array and support regions of the chip, and ideally would require different processes during manufacturing. For example, junctions with self-aligned silicides (e.g., salicides) are desired in the support regions to minimize series resistance. On the other hand, shallow junctions with low dose implants and no silicides are typically desired in the array in order to minimize junction leakage.
As another example, during conventional processing of the array for DRAM/eDRAM with vertical array devices, an array top oxide is deposited and certain portions are thereafter removed. Generally, the array top oxide is removed entirely from the support array. See, for example, R. Divakaruni, et al. “In ULSI Process Integration II”, Electrochemical Society Proceeding Col. 2, 2001. However, existing wet etch processes may cause shallow trench isolation areas within the support area to be exposed to overetching which, in turn, may lead to voids at the trench edges, gate shorts and the like.
As indicated above, array top oxides including oxynitrides are known to be used in the fabrication of semiconductor memory with vertical array devices. See, for example, U.S. Pat. No. 6,509,226 to Jaiprakash, et al., U.S. Pat. No. 6,635,526 to Malik, et al., U.S. Pat. No. 6,727,540 to Divakaruni, et al., U.S. Pat. No. 6,787,838 to Chiadambarrao, et al., and U.S. Pat. No. 6,790,739 to Malik, et al. as well as U.S. Printed Application Publication No. 2003/0143809 A1 to Hummler. Although various processes of fabricating semiconductor memory devices that include array top oxides are known, processes that use array top oxides add additional processing steps, and thus cost to the overall manufacturing process.
A method of fabricating semiconductor structures comprising vertical array semiconductor memory devices such as DRAMs and eDRAMs is needed which avoids the use of an array top oxide. Such a method would simplify the fabrication of semiconductor structures including vertical array semiconductor memory devices, and thus reduce the overall production cost of fabricating the same.